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W83791D winbond h/w monitoring ic
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 i W83791D data sheet revision history pages dates version version on web main contents 1 n.a. n.a. all version before 0.20 are for internal use. 2 n.a. 01/jan 0.2 n.a. first publication. 3 p.7 01/jan 0.21 n.a. re vise slotocc# pin description. 4 p.34 01/jan 0.21 n.a. add smi# /irq for voltage/fan description. 5 p.43/44 19/mar 0.3 n.a. register index 1ah~1fh revised. 6 p. 40 p. 42 p. 60/61 p. 58/59 p. 66 p. 66 p. 66 p. 87 21/may 0.4 n.a. thi s update is for c version ic. 1) add evntrap1 - 5 polarity (index ah ) 2) add vid protection control bit (index15h bit5) 3) add fan1 - 3/pwmout1 - 3 as gpin data register. (index 95h/97h) 4) smartfan tm step up/down time registers exchanged. 5) add a bit (index a6 bit7) to kn ow either speech or gpio function did you use. 6) pin44 (smi#/ledout) is a multi - function, it is programmable. 7) eventrap can as gpio by programming index a6h bit0 - 4 . 8) updated v0.17 schematics adding ledout circuit for smi# (pin 44) 7 all pages 09/aug 0.41 n. a. repaginate datasheet please note that all data and specifications are subject to change without notice. all the trademarks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these produ cts are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so a t their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 ii table of contents 1. general description ................................ ................................ ................................ .... 1 2. features ................................ ................................ ................................ ........................... 3 2.1 monitoring items ................................ ................................ ................................ ................................ . 3 2.2 address resolution protocol (arp) and alert - standard forum(a sf) ................................ ................... 3 2.3 speech items ................................ ................................ ................................ ................................ ....... 3 2.4 actions enabling ................................ ................................ ................................ ................................ . 3 2.5 enhance moni toring vid function ................................ ................................ ................................ ....... 4 2.6 general ................................ ................................ ................................ ................................ ................ 4 2.7 package ................................ ................................ ................................ ................................ ............... 4 3. key specifi cations ................................ ................................ ................................ ......... 4 4. pin configuration ................................ ................................ ................................ .......... 5 5. pin description ................................ ................................ ................................ ................ 6 6. functio n description ................................ ................................ ................................ .. 10 6.1 general description ................................ ................................ ................................ ........................... 10 6.2 access interface ................................ ................................ ................................ ................................ 10 6.2.1 the first serial bus access timing ................................ ................................ ............ 10 6.3 speech function ................................ ................................ ................................ ................................ 11 6.3.1 general description ................................ ................................ ................................ . 11 6.3.2 event trigger queue ................................ ................................ ............................... 11 6.3.3 connection of eeprom ................................ ................................ .......................... 12 6.3.4 speaker output ................................ ................................ ................................ ....... 13 6.4 address resolution protocol (arp) introduction ................................ ................................ ............... 14 6.5 asf(alert standard format) introduction ................................ ................................ .......................... 16 6.5.1 platform event trap (pet) ................................ ................................ ....................... 16 6.6 analog inputs ................................ ................................ ................................ ................................ .... 19 6.6.1 monitor over 4.096v voltage: ................................ ................................ ................... 19 6.6.2 monitor negative voltage: ................................ ................................ ......................... 20 6.7 fan speed count and fan speed control ................................ ................................ ........................ 21 6.7.1 fan speed count ................................ ................................ ................................ ...... 21 6.7.2 fan speed control ................................ ................................ ................................ .... 22 6.7.3 smart fan control ................................ ................................ ................................ ... 23 6.8 temperature measurement machine ................................ ................................ ................................ .. 25 6.8.1 monitor temperature from thermistor: ................................ ................................ ....... 25 6.8.2 monitor tem perature from pentium ii tm thermal diode or bipolar transistor 2n3904 ... 25 6.8.3 smi# interrupt for W83791D voltage ................................ ................................ ........ 26 6.8.4 smi# interrupt for W83791D fan ................................ ................................ ............. 26 6.8.5 smi# interrupt for W83791D temperature sensor 1/2/3 ................................ ................................ ................................
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 iii 6.8.6 over - temperature (ovt#) for w837 91d temperature sensor 1/2/3 .......................... 28 7 control and status r egister ........................ error! bookmark not defined. 7.1 speech flash memory address registers ? index 00h - 02h (bank 0) ... error! bookmark not defined. 7.2 speech flash memory data registers ? index 03h - 06h (bank 0) ........ error! bookmark not defined. 7.3 speech flash memory control register ? index 07h ( bank 0) ............ error! bookmark not defined. 7.4 event trigger timeout register ? index 08h (bank 0) ........................ error! bookmark not defined. 7.5 speech programmable trigger register ? index 09h (bank 0) ............ error! bookmark not defined. 7.6 speech input trigger property register ? index 0ah (bank 0) ............ error! bookmark not defined. 7.7 reserved register ? index 0bh (bank 0) ................................ ............ error! bookmark not de fined. 7.8 vid and vcore voltage property register ? index 0ch (bank 0) ..... error! bookmark not defined. 7.9 speech flash memory read data registers ? index 0dh - 0eh (bank 0) error! bookmark not defined. 7.10 reserved register ? index 0fh (bank 0) ................................ ............ error! bookmark not defined. 7.11 vid control/status register ? index 10h (bank 0) ............................. error! bookmark not defined. 7.12 entry disable vid output control register ? index 11h (bank 0) ...... error! bookmark not defined. 7.13 vid output tolerance/limit register ? index 12h (bank 0) ............... error! bookmark not defined. 7.14 gpio control register i ? index 13h (bank 0) ................................ ... error! bookmark not defined. 7.15 gpio data/status register i ? index 14h (bank 0) ............................. error! bookmark not defined. 7.16 gpio control register ii ? index 15h (bank 0) ................................ .. error! bookmark not define d. 7.17 gpio output data and status register ii ? index 16h (bank 0) .......... error! bookmark not defined. 7.18 led control register ? index 17h (bank 0) ................................ ....... error! bookmark not defined. 7.19 user defined registers ? index 18h - 1ch (bank 0) ............................. error! bookmark not defined. 7.20 speech control register 1 -- index 1dh (bank 0) ................................ .. error! bookmark not defined. 7.21 speech control register 2 -- index 1eh ( bank 0 ) ................................ .. error! bookmark not defined. 7.22 speech control register 3 -- index 1fh ( bank 0 ) ................................ ... error! bookmark not defined. 7.23 value ram ? index 20h - 3fh (bank 0) ................................ .............. error! bookmark not defined. 7.24 configuration register ? index 40h (bank 0) ................................ ..... error! bookmark not defined. 7.25 interrupt status register 1 ? index 41h (bank 0) ................................ error! bookmark not defined. 7.26 interrupt status register 2 ? index 42h (bank 0) ................................ er ror! bookmark not defined. 7.27 smi# mask register 1 ? index 43h (bank 0) ................................ ...... error! bookmark not defined. 7.28 smi# mask register 2 ? index 44h (bank 0) ................................ ...... error! bookmark not defined. 7.29 irq mask register 1 ? index 45h (bank 0) ................................ ........ error! bookmark not defined. 7.30 irq mask register 2 ? index 46h (bank 0) ................................ ........ error! bookmark not defined. 7.31 vid/fan divisor register ? index 47h (bank 0) ................................ . error! bookmark not defined. 7.32 serial bus address register ? index 48h (bank 0) .............................. error! bookmark not defined. 7.33 voltage id (vid4) & device id -- index 49h (bank 0) ........................ error! bookmark not defined. 7.34 temperature 2 and temperature 3 serial bus address register -- index4ah (bank 0) error! bookmark not defined. 7.35 pin control register -- index4bh (bank 0) ................................ ........... error! bookmark not defined. 7.36 smi#/ovt# property select -- index 4ch (bank 0) ............................. error! bookmark not defined. 7.37 fan 1 - 3 in/out and beep control register -- index 4dh (bank 0) .. error! bookmark not defined. 7.38 bank select -- index 4eh (bank 0) ................................ ....................... error! bookmark not defined. 7.39 winbond vendor id -- in dex 4fh (bank 0) ................................ .......... error! bookmark not defined. 7.40 winbond test register -- index 50h - 55h (bank 0) .............................. error! bookmark not defined. 7.41 beep control register 1 -- index 56h (bank 0) ................................ .... error! bookmark not defined.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 iv 7.42 beep control register 2 -- index 57h ( bank 0 ) ................................ ..... error! bookmark not defined. 7.43 chip id -- index 58h ( bank 0 ) ................................ ............................. error! bookmark not defined. 7.44 diode selection register -- index 59h (bank 0) ................................ ... error! boo kmark not defined. 7.45 reserved -- index 5ah - ( bank 0 ) ................................ ........................ error! bookmark not defined. 7.46 fanin 4/5 control -- index 5bh (bank 0) ................................ .......... error! bookmark not defined. 7.47 fan 4/5 divisor control -- index 5ch (bank 0) ................................ . error! bookmark not defined. 7.48 vbat monitor contr ol register -- index 5dh ( bank 0 ) ....................... error! bookmark not defined. 7.49 acpi temperature increment register -- index 5eh ............................. error! bookmark not defined. 7.50 reserved -- index 5fh ( bank 0 ) ................................ ........................... error! bookmark not defined. 7.51 fan 1 pre - scale register -- index 80h (bank 0) ................................ ... error! bookmark not defined. 7.52 fan 1 duty cycle select register -- 81h ( bank 0 ) ................................ error! bookmark not defined. 7.53 fan 2 pre - scale register -- index 82h (bank 0) ................................ ... error! bookmar k not defined. 7.54 fan2 duty cycle select register -- index 83h (bank 0) ....................... error! bookmark not defined. 7.55 fan 1/2 configuration register -- index 84h (bank 0) .......................... error! bookmark not defined. 7.56 fan 1 target temperature register/target fan 1 speed control register -- index 85h (bank 0) ... error! bookmark not defined. 7.57 fan 2 target temperature register/target fan 2 speed control register -- index 86h (bank 0) .... error! bookmark not defined. 7.58 tolerance of fan 1/2 target temperature or speed register -- index 87h (bank0) error! bookmark not defined. 7.59 fan 1 pwm stop duty cycle register -- index 88h (bank 0) ................ error! bookmark not defined. 7.60 fan 2 pwm stop duty cycle register -- 89h ( bank 0 ) ......................... error! bookmark not defined. 7.61 fan 1 start - up duty cycle register -- index 8ah (bank 0) ................... error! bookmark not defined. 7. 62 fan 2 start - up duty cycle register -- index 8bh (bank 0) .................... error! bookmark no t defined. 7.63 fan 1 stop time register -- index 8ch (bank 0) ................................ .. error! bookmark not defined. 7.64 fan 2 stop time register -- index 8dh (bank 0) ................................ .. error! bookmark not defined. 7.65 fan 1/2/3 step down time register -- index 8eh (bank 0) ................... error! bookmark not defined. 7.66 fan 1/2/3 step up time register -- index 8fh (bank 0) ....................... error! bookmark not defined. 7.67 temperature sensor 1 (vtin1) offset register - index 90h (bank 0) ... error! bookmark not defined. 7.68 temper ature sensor 2 (vtin2) offset register - index 91h (bank 0) ... error! bookmark not defined. 7.69 temperature sensor 3 (vtin3) offset register - index 92h (bank 0) ... error! bookmark not defined. 7.70 fan 3 pre - scale register -- index 93h (bank 0) ................................ ... error! bookmark not defined. 7.71 fan 3 duty cycle select register -- 94h ( bank 0 ) ................................ error! bookmark not de fined. 7.72 fan 3 configuration register -- index 95h (bank 0) ............................. error! bookmark not defined. 7.73 fan 3 target temperature register/target fan 3 speed control register -- index 96h (bank 0) ... error! bookmark not defined. 7.74 tolerance of fan 3 target temperature or speed register -- index 97h (bank 0) error! bookmark not defined. 7.75 fan 3 pwm stop duty cycle register -- index 98h (bank 0) ................ error! bookmark not defined. 7.76 fan 3 start - up duty cycle register -- index 99h (bank 0) .................... error! bookmark not defined. 7.77 fan 3 stop time register -- index 9ah (bank 0) ................................ .. error! bookmark not defined. 7.78 interrupt status register iii -- index 9bh (bank 0) ............................... error! bookmark not defined. 7.79 smi# mask register iii -- index 9ch (bank 0) ................................ ..... error! bookmark not defined. 7.80 interrupt mask register iii -- index 9dh (bank 0) ................................ error! bookmark not define d. 7.81 fan4_pre_scale register -- index 9eh ( bank 0 ) .............................. error! bookmark not defined. 7.82 fan5_pre_scale register -- index 9fh ( bank 0 ) .............................. error! bookmark not defined.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 v 7.83 fan 4 duty cycle select register ? a0h ( bank 0 ) ............................... error! bookmark not defined. 7.84 fan 5 duty c ycle select register ? a1h ( bank 0 ) ............................... error! bookmark not defined. 7.85 beep control register 3 -- index a3h ( bank 0 ) ................................ .... error! bookmark not defined. 7.86 speech flash memory read data reg isters ? index a4h - a5h (bank 0) error! bookmark not defined. 7.87 evntrap1 - 5 and gpio 5 - 9 select -- index a6h (bank 0) ................ error! bookmark not defined. 7.88 flash page count -- inde x a7h ( bank 0 ) ................................ .............. error! bookmark not defined. 7.89 real time hardware status register i -- index a9h ( bank 0 ) ............... error! bookmark not defined. 7.90 real time hardware status register ii -- index aah ( bank 0 ) ............. er ror! bookmark not defined. 7.91 real time hardware status register iii -- index abh ( bank 0 ) ............ error! bookmark not defined. 7.92 revered -- index ac - afh ( b ank 0 ) ................................ ................... error! bookmark not defined. 7.93 value ram 2 ? index b0h ? b7h (bank 0) ................................ ....... error! bookmark not defined. 7.94 temperature sensor 2 temperature (high byte) register - index c0h ( bank 0 ) error! bookmark not defined. 7.95 temperature sensor 2 temperature (low byte) register - index c1h ( bank 0 ) error! bookmark not defined. 7.96 temperature sensor 2 configura tion register - index c2h ( bank 0 ) ..... error! bookmark not defined. 7.97 temperature sensor 2 hysteresis (high byte) register - index c3h ( bank 0 ) error! bookmark not defined. 7.98 tem perature sensor 2 hysteresis (low byte) register - index c4h ( bank 0 ) error! bookmark not defined. 7.99 temperature sensor 2 over - temperature (high byte) register - index c5h ( bank 0 ) error! bookmark not defined. 7.100 temperature sensor 2 over - temperature (low byte) register - index c6h( bank 0 ) error! bookmark not defined. 7.101 temperature sensor 3 temperature (high byte) register - index c8h ( bank 0 ) error! bookmark not defined. 7.102 temperature sensor 3 temperature (low byte) register - index c9h ( bank 0 ) error! bookmark not defined. 7.103 temperature sensor 3 config uration register - index cah ( bank 0 ) .... error! bookmark not defined. 7.104 temperature sensor 3 hysteresis (high byte) register - index cbh ( bank 0 ) error! bookmark not defined. 7.10 5 temperature sensor 3 hysteresis (low byte) register - index cch ( bank 0 ) error! bookmark not defined. 7.106 temperature sensor 3 over - temperature (high byte) register - index cdh ( bank 0 ) error! bookmark not defined. 7.107 temperature sensor 3 over - temperature (low byte) register - index ceh( bank 0 ) error! bookmark not defined. 8 arp (address resolut ion protocol) use re gister defined error! boo kmark not defined. 8.1 unique device identifier (udid) -- 20h - 2fh ( bank 1 ) ......................... error! bookmark not defined. 8.2 asf sensor environmental event ................................ ........................ error! bookmark not defined. 8.2.1 temperature: get event data message ...................... error! bookmark not defined. 8.2.2 voltage: get event data message .............................. error! bookmark not defined. 8.2.3 fan: get event data message ................................ .... error! bookmark not defined. 8.2.4 case intrusion: get event data message .................... error! bookmark not defined. 8.3 asf response registers -- 40h - 7fh ( bank 1 ) ................................ ....... error! bookmark not defined. 8.3.1 asf upper/lower temperature registers: .................. error! bookmark not defined. 8.3.2 sensor device: (smbus address, read/write) error! bookmar k not defined.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 vi 8.3.3 relative entity id table: ................................ ............. error! bookmark not defined. 8.3.4 default entity id ................................ .......................... error! bookmark not defined. 8.3.5 entity instance register ................................ .............. error! bookmark not defined. 8.4 bjt rt - table - 50h - 57h ( bank 7 ) ? test mode only .......................... error! bookmark not defined. 9 electrical character istics ................................ ................................ .................... 30 9.1 absolute maximum ratings ................................ ................................ ................................ ............... 30 9.2 dc characteristics ................................ ................................ ................................ ............................. 30 9.3 ac characteristics ................................ ................................ ................................ ............................. 32 9.3.1 serial bus timing diagram ................................ ................................ ...................... 32 10 how to read the top marking ................................ ................................ ................. 33 11 package specific ation ................................ ................................ ............................... 34
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 1 1. general description W83791D is an evolving version of the w83 782 d --- winbond's most popular hardware status monitoring ic. besides the conventional functions of w83782d, W83791D uniquely provides several innovat ive features such as speech function, asf sensor compliant, smbus 2.0 arp command compatible, vid table selection trapping, and 5vid output control. conventionally, W83791D can be used to monitor several critical hardware parameters of the system, includin g power supply voltages, fan speeds, and temperatures, which are very important for a high - end computer system to work stably and efficiently. as for data access, W83791D provides slave smbus 2.0 interface which can reply pec (packet error code) when as as f sensor. an 8 - bit analog - to - digital converter (adc) was built inside W83791D. W83791D can simultaneously monitor 10 analog voltage inputs (including power vdd/5vsb monitoring), 5 fan tachometer inputs, 3 remote temperatures, and one case open detection s ignal. the sense of remote temperature can be performed by thermistors, 2n3904 npn - type transistors, or directly from intel tm cpu with thermal diode output. W83791D provides 3 pwm (pulse width modulation) outputs for two modes of smart fan control - } therm al cruise tm ~ mode and } speed cruise } mode. under } thermal cruise tm ~ mode, temperatures of cpu and the system can be maintained within specific programmable ranges under the hardware control. } speed cruise } , namely, is to keep the fan operate in the spec ific programmable r.p.m . as for warning mechanism, W83791D provides speech voice warning, beep tone warning, and smi#, ovt#, irq signals for system protection events. additionally, 5 vid inputs are provided to read the vid of cpu (i.e. pentium tm i i/ii i) if applicable. these vid inputs provide the information of vcore voltage that cpu expects. furthermore, W83791D provides programmable vid output control to alter the voltage cpu consumes. W83791D also uniquely provides an optional feature: early stage ( before bios was loaded) beep / speech warning to detect if the fatal elements present --- vcore or +3.3v voltage fail and thus the system can not be boomed up. if the vsb power on setting refers to intel vrm 9.x, the vid table within W83791D will be accor ding to the new one. W83791D also has 2 specific pins to provide selectable address setting for application of multiple devices (up to 4 devices) wired through i 2 c tm interface. W83791D speech function is enabled by building in a programmable speech synth esizer with a 9 - bit current dac output as well as a connectable external flash memory for storing voice data. W83791D supports 1 cpu present or absent event trap, 5 external event traps, 17 hardware monitor event traps (10 analog voltage, 3 fan tachometer, 3 remote temperature, 1 case open) and 128 internal programmable event traps, amounting to 151 different speech outputs. if more than two events happen simultaneously, the priority set is: slotocc# > evntrp1 > evntrp2 > evntrp3 > evntrp4 > evntrp5 > 128 programmable events (bank0 index 09h) > 17 hardware status events. voice data stored in the external flash memory interface with winbond w55fxx is flexible to change by winbond application software and on - line programming flash data is provided also. besi des, an external resistor is added to provide ring oscillator. when you do not use the speech function, W83791D provides a set of flexible i/o control functions to the system designer through a set of general purpose i/o ports. these gpio ports may serve as simple i/o or may be individually configured to provide a pre - defined alternate function. if pin 9 (speech_sel) is trapped to high at vsb power on, this function will be active. W83791D can uniquely serve as an asf sensor to respond to asf master?s req uest for the implementation of network management in os - absent state. through W83791D?s compliance with asf sensor spec , network server is able to monitor the environmental status of the client in os - absent state by pet frame values returned from W83791D, such as temperatures, voltages, fan speed, and case open. moreover, W83791D supports smbus 2.0 arp command to solve the problem of address conflicts by dynamically assigning a new unique address to W83791D after W83791D?s udid is sent. through the appli cation software or bios, the users can read all the monitored parameters of the system
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 2 from time to time. a pop - up warning can also be activated when the monitored item is out of the proper/preset range. the application software could be winbond's hard ware doctor tm , intel tm ldcm (landesk client management), or other management application software. besides, the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and activate one programmable and maskable interr upts. an optional beep tone could be used as a warning signal when the monitored parameters are out of the preset range.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 3 2. features 2.1 monitoring items 10 voltage inputs --- typical for vcore, +3.3v, +12v, - 12v, +5v, - 5v, +5vsb, vbat, and two reserved 5 fan speed monitoring inputs 3 temperature inputs from remote thermistors, 2n3904 npn - type transistors or pentium tm ii (deschutes) thermal diode output case open detection input watchdog comparison of all monitored values programmable hysteresis and setting points (alarm thresholds) for all monitored items 2.2 address resolution protocol (arp) and alert - standard forum(asf) support system management bus (smbus) version 2.0 specification comply with hardware sensor slave arp (address resolution protocol) response sensor type arp command response asf command --- get event data , get event status comply with asf sensors (monitoring fan speed, voltage, temperature, and case open) 2.3 speech items programmable speech synthesizer with new high fidelity synthesis algorith m build in 8 - bit current d/a converter 1 cpu present or absent trigger input 5 external trigger inputs 128 internal programmable trigger inputs 17 h/w monitor event trigger inputs programmable 0 - 255 seconds timeout trigger inputs for firmware or software instruction cycle is ?? 400 g s typically section control provided in each voice section external resistor for ring oscillator 2.4 actions enabling beep tone warning separated speech output 5 pwm (pulse width modulation) outputs for fan speed control (1~3 support smart fan control) and 5 fan speed inputs for monitoring --- total up to 5 sets of fan speed monitoring and controlling issue smi#, ovt#, irq signals to activate system protection warning signal pop - up in application software
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 4 2.5 enhance monitoring vid function cpu voltage id reading vid output control enhance beep warning by detecting i ntel vrm 9.0 vid 2.6 general i 2 c tm serial bus interface 5 vid input pins for cpu vcore identification (for pentium tm ii/iii) initial power fault beep (for +3.3v, vcore) 2 pins (a0, a1) to provide selectable address setting for application of multiple devices (up to 4 devices) wired through i 2 c tm interface winbond hardware monitoring application software (hardware doctor tm ) support, for both windows 95/98/2000 and windows nt 4.0/5.0 internal clock oscillator with 3m hz 5v vsb operation 2.7 package 48 - pin lqfp 3. key specifications voltage monitoring accuracy 1% (max) intel vrm 9.x voltage monitoring accuracy 0.5% (max) monitoring temperature range and accuracy - 40 c to +120 c 3 c(max) supply voltage 5v operating supply current 5 ma typ. adc resolution 8 bits
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 5 4. pin configuration g n d d s c l s d a r e x t p w m o u t 2 / a 1 p w m o u t 1 / a 0 a d d r / g p i o 0 W83791D 1 12 13 24 25 36 37 48 v c o r e v i n r 0 + 3.3 v i n v i n r 1 + 12 v i n - 12 v i n v b a t + 5 v s b - 5 v i n g n d a v i d 3 caseopen b e e p smi#/led ovt# vid0 vtin1/piitd1 vtin3/piitd3 vtin2/piitd2 vref vid4 fanin3 fanin2 fanin1 pwmtout3/vid_v90 vidin2 c l k o u t / g p i o 1 d a t a / g p i o 2 c t r l / g p i o 3 m o d e / g p i o 4 e v n t r p 5 / g p i o 9 / p w m o u t 5 evntrp1/gpio5 e o p s p e a k e r / l e d / s p e e c h _ s e l v i d 1 slotocc# irq/gpio10 evntrp2/gpio6/fanin4 evntrp3/gpio7/fanin5 evntrp4/gpio8/pwmout4 47 46 45 44 43 42 41 40 39 38 2 3 4 5 7 6 8 9 10 11 14 15 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 33 34 35 vdd
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 6 5. pin description i/o 12t - ttl level bi - directional pin with 12 ma source - sink capability i/o 12ts - ttl level and schmitt trigger with 12 ma source - sink capability i/o 8ts - ttl level and schmitt trigger with 8 ma source - sink capability i/o 6ts - ttl level and schmitt trigger with 6 ma source - sink capability i/od 12ts - ttl level and schmitt trigger open drain output with 12 ma sink capability out 12 - output pin with 12 ma source - sink capability od 12 - open - drain output pin with 12 ma sink capability aout - output pin(analog) in t - ttl level input pin in ts - ttl level input pin and schmitt trigger ain - input pin(analog) pin name pin no. type description evntrp5 / 1 i /o 12t event trapping to selection speech output sound. default is high edge trigger. gpio9/ pwmout5 general purpose i/o function. if pin 9 (speech_sel) is trapped to high at vsb power on, this function wi ll be active. the i/o control and status is defined in bank0 index 13h~14h. otherwise, gpio pin or pwmout fan control can be selected by registers, but the pwmout can not support smart fan. eop 2 i end of process signal input from cascaded flash. gpio1 1 i/od 12ts general purpose i/o function pin. if pin 9 (speech_sel) is trapped to high at vsb power on, this function will be active. rext 3 i resistor(rosc) connect to vsb used to adjust ring oscillator frequency. addr / 4 out 12 speech address pulse output, connect to w55fxx. when this pin translates from logic high to logic low, it will latch the data pin 6 and shift it into a speech flash address counter. gpio0 i/od 12ts general purpose i/o function. if pin 9 (speech_sel) is trapped to high at vsb power on, this function will be active. clkout / 5 out 12 speech clock output, for speech data read - out and write - in, connect to w55fxx. when this pin translates from logic high to logic low, the data pin 6 will be latched by this clock. gpio1 i/od 12t s general purpose i/o function. if pin 9 (speech_sel) is trapped to high at vsb power on, this function will be active. data / 6 i/o 12t serial data input/output, connect to w55fxx. the pin is latched by clkout and addr acted as speech data and address res pectively. gpio2 i/od 12ts general purpose i/o function. if pin 9 (speech_sel) is trapped to high at vsb power on, this function will be active. ctrl / 7 out 12 output clock numbers of this pin decide which mode is selected. connect to w55fxx. gpio3 i /od 12ts general purpose i/o function. if pin 9 (speech_sel) is trapped to high at vsb power on, this function will be active. mode / 8 out 12 output mode signal to w55fxx serial flash.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 7 gpio4 i/od 12ts general purpose i/o function. if pin 9 (speech_sel) is trapped to high at vsb power on, this function will be active. speaker 9 out 12 current type output driving an external speaker. the function is only working in vdd 5v ok. led out 12 led output control. this is a multi - function pin with speaker. when t he led_sel register (bank0 index 17h) is set to 1, led output function will be active. otherwise, set to 0 (default), this pin serves as speaker output. speech_sel in ts during vsb 5v power on, this pin is used to trap whether using speech function or gpi o function. trapping low means using speech function (i.e. pin45 - 48, pin1, pin4 - 8 are as speech function). trapping high means using gpio function (i.e. pin45 - 48, pin1, pin4 - 8 are as gpio function). the i/o control and status is defined in bank0 index 13 h~16h. pwmout1/ 10 out 12 fan speed control pwm output. when the power of vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. a0 in ts i 2 c device address bit0 trapping during 5vsb power on. pwmout2 / 11 out 12 fan speed control pwm output. when the power of vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. a1 in ts i 2 c device address bit1 trapping during 5vsb power on. vid1 12 i /o 12ts voltage supply readouts from cpu. after programmi ng, this pin can be vid output to voltage regulator to generate vcore for cpu. vdd (5v) 13 power +5v vdd power. bypass with the parallel combination of 10 m f (electrolytic or tantalum) and 0.1 m f (ceramic) bypass capacitors. gndd 14 dground internally con nected to all digital circuitry. slotocc# 15 in ts cpu presence signal. 0, means cpu is present. 1, means cpu is absent. caseopen 16 i/o 6ts case open detection. an active high input from an external device when case is intruded. this signal can be lat ched in external circuit which power is supplied by vbat, even if W83791D is power off. vid4 17 i /o 12ts voltage supply readouts from cpu. after programming, this pin can be vid output to voltage regulator to generate vcore for cpu. fan3in - fan1in 18 - 2 0 in ts 0v to +5v amplitude fan tachometer input scl 21 in ts serial bus clock. sda 22 i/od 8ts serial bus bi - directional data. pwmout3 / 23 out 12 fan speed control pwm output. when the power of vdd is 0v, this pin will drive logic 0. the power of this pin is supplied by vsb 5v. vid_v90 in ts vid table selection trapping during rsmrst (0: intel vrm 8.2/8.3; 1: intel vrm 9.0). when the trapping pin get a logic 1, the beep warning function is according to intel vrm 9.0 vid. vid2 24 i /o 12ts voltage su pply readouts from cpu. after programming, this pin can be vid output to voltage regulator to generate vcore for cpu. vid3 25 i /o 12ts voltage supply readouts from cpu. after programming, this pin can be vid output to voltage regulator to generate vcore for cpu.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 8 beep 26 od 12 alarm beep output. normal, this pin is low. when abnormal event happens, this pin will output alarm frequency. gnda 27 aground internally connected to all analog circuitry. the ground reference for all analog inputs. - 5vin 28 ai n 0v to 4.096v fsr analog inputs. +5vsb 29 power this pin is power for W83791D. bypass with the parallel combination of 10 m f (electrolytic or tantalum) and 0.1 m f (ceramic) bypass capacitors. vbat 30 power this pin is power for W83791D. - 12vin 31 ai n 0 v to 4.096v fsr analog inputs. +12vin 32 ai n 0v to 4.096v fsr analog inputs. vinr1 33 ai n 0v to 4.096v fsr analog inputs. +3.3vin 34 ai n 0v to 4.096v fsr analog inputs. vinr0 35 ai n 0v to 4.096v fsr analog inputs. vcore 36 ai n 0v to 4.096v fsr analog inputs. vref 37 aout reference voltage. vtin3 / 38 ai n thermistor 3 terminal input.(default). piitd3 pentium tm ii diode 3 input. this multi - functional pin is programmable. vtin2 / 39 ai n thermistor 2 terminal input. (default). piitd2 pentium tm ii diode 2 input. this multi - functional pin is programmable. vtin1 / 40 ai n thermistor 1 terminal input. (default). piitd1 pentium tm ii diode 1 input. this multi - functional pin is programmable. vid0 41 i /o 12ts voltage supply readouts from cpu. afte r programming, this pin can be vid output to voltage regulator to generate vcore for cpu. ovt# 42 od 12 over temperature shutdown output for temperature sensor 1 - 3. irq / 43 out 12 interrupt request. gpio10 i/od 12ts general purpose i/o function. if pi n 9 (speech_sel) is trapped to high at vsb power on, this function will be active. smi# / 44 od 12 system management interrupt (open drain). led out 12 led output control. this is a multi - function pin with smi. when the register (bank0 index 17h bit7 an d index a6h bit 6) is set to 1, led output function will be active. otherwise, set to 0 (default), this pin serves as smi#. evntrp2 - 3 / 46 - 47 i/o 12ts event trapping to selection speech output sound. default is high edge trigger. gpio6 - 7/ fanin4 - 5 i/o 12ts general purpose i/o function. if pin 9 (speech_sel) is trapped to high at vsb power on, this speech function will be active. the i/o control and status is defined in bank0 index 13h~14h. otherwise, gpio pin or fan inputs can be selected by registers. ev ntrp4 / 48 i/o 12ts event trapping to selection speech output sound.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 9 gpio8/ pwmout4 i/o 12ts general purpose i/o function. if pin 9 (speech_sel) is trapped to high at vsb power on, this function will be active. the i/o control and status is defined in bank0 index 13h~14h. otherwise, gpio pin or pwmout fan control can be selected by registers, but the pwmout can not support smart fan.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 10 6. function description 6.1 general description the W83791D provides 10 analog positive inputs, 5 fan speed inputs , at most 5 se ts for fan pwm (pulse width modulation) control, 3 thermal inputs from remote thermistors ?b 2n3904 transistors or pentium tm ii/iii (deschutes) thermal diode outputs, case open detection and beep function output when the monitored values exceed preset ranges , including the voltage, temperature, and fan count. moreover, W83791D uniquely provid es several innovative and practical functions to make the whole system more efficient and compliant with future trend of network management, such as speech function, asf sensor compliant, smbus 2.0 arp command compatible, vid table selection trapping, 5vi d output control, and so forth. once the monitoring function ofW83791D is enabled, the watch dog machine will monitor every function and store the values to registers for comparison with preset ranges. if the monitoring value exceeds the limit value, the i nterrupt status will be set to 1 and W83791D will issue interrupt signals such as smi# and irq if not masked.. 6.2 access interface the W83791D provides i 2 c serial bus for microprocessor to read/write internal registers. in the W83791D, there are three serial bus addresses. through the first address defined at cr[48h], all the registers can be read and written except cput1/cput2 temperature sensor registers. the read/write of the cput1/cput2 temperature sensor registers can be implemented through the second address (defined at cr[4ah] bit2 - 0) and the third address (defined at cr[4ah] bit6 - 4). the first serial bus address of W83791D has 2 hardware setting bits set by pin10 - 11. the address is 001011[pin11][pin10]. hence, the content of cr[48h] would be 001011 10 if pin11=1 and pin10=0 . 6.2.1 the first serial bus access timing (a) serial bus write to internal address register followed by the data byte 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 ack by 791d r/w ack by 791d scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack by 784r stop by master scl sda (continued) 7 8 0 7 8 0 7 8 frame 2 internal index register byte (continued) frame 3 data byte frame 1 serial bus address byte figure 1. serial bus write to internal address register followed by the data byte ack by 791d
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 11 (b) serial bus read from a register 0 d7 d6 d5 d4 d3 d2 d1 d0 ack by master ack by 791d scl sda 7 8 0 7 8 0 frame 4 data byte frame 3 serial bus address byte figure 2. serial bus read from internal address register stop by master 0 start by master 0 1 0 1 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 r/w ack by 791d scl sda 7 8 0 7 8 0 frame 2 internal index register byte frame 1 serial bus address byte ack by 791d (continued) (continued) 0 1 0 1 1 0 1 r/w repeat start by master 6.3 speech function 6.3.1 ge neral description the W83791D is a derivative of winbond's powerspeech tm synthesizers. there are up to 5 hardware trigger inputs, 17 hardware monitor event and 128 programmable software event trigger inputs. if more than two events happen simultaneously, t he priority set by the internal h/w is: slotocc# > evntrap1 > evntrap2 > evntrap3 > evntrap4 > evntrap5 > trigreg(index 09h) 128 events > vin0 > vin1> others (vin2 ? vin9,temp, fan, case open). software trigger is able to accommodate 128 event triggers, wit h timeout register (index 08h) enabled in advance for allowance of time on detecting devices. that is, once the system?s power is on, bios can fill trigger event and speech voice will not be sent till the system fails owing to timeout. in addition, to prev ent events from taking place simultaneously. 6.3.2 event trigger queue W83791D provides 8 byte fifo queue to store event trigger, i.e, the first 8 event can be served by speech and speech will clear fifo queue after service. coding of speech program must assign correct cpu_mode event vector to issue correct speech voices correspondent to speech trigger events. for example, cpu_mode event vector =1 represents absence of cpu, then coding speech with cpu is absent voice. when W83791D detects no cpu exists, it will s end vector = 1 to speech synthesizer and play this voice data. following is the block diagram of the 8 - byte event trigger queue. 8-bit counter trigger timeout register clk 1 hz timeout comparator trig_reg event trigger data enable timeout 8-byte event trigger queue (index 08h) (index 09h, b6~0) (index 0ah, b6) figure 3. event trigger queue
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 12 for example: as bios usually has post (power on self test) program, then it will test every item step by step if no failure takes place, however, if it detects a failure on a specific item, it will hang on there. therefore, bios could write timeout value to register 08h and start timer setup speech trigger event (register 09h), then is bios test program star ted. whenever the system is hang on specific item such as dram testing, W83791D would say ?dram test fails? after the timeout previously set at cr[08h]. on the contrary, if dram test is ok, then bios could update the timeout value and proceed to the next test program. below is the speech cpu_mode table of W83791D : cpu_mode item definition vector (h) poi reserverd 0,32 slotocc cpu present or absent 1 evntrap1(tg1) hardware trgger1 2 evntrap2 hardware trgger2 3 evntrap3 hardware trgger3 4 evntrap4 hardware trgger4 5 evntrap5 hardware trgger5 6 trigreg i2c setting software trigger 80 - ff in0 vcore(vin0 ) exceed limit 40 in1 vinr0(vin1) exceed limit 41 in2 (+3.3vin)vin2 exceed limit 42 in3 (5vdd)vin3 exceed limit 43 in4 (+12vin)vin4 exceed limi t 44 in5 ( - 12vin)vin5 exceed limit 45 in6 ( - 5vin)vin6 exceed limit 46 in7 vsb(vin7) exceed limit 47 in8 vbat(vin8 ) exceed limit 48 in9 (vinr1)vin9 exceed limit 49 temp1 vtin1 exceed limit 4a temp2 vtin2 exceed limit 4b temp3 vtin3 exceed limit 4c fan1 fan1 count over limit 4d fan2 fan2 count over limit 4e fan3 fan3 count over limit 4f chs_ev case open trigger 50 table 1. cpu_mode table 6.3.3 connection of eeprom as is described previously that the W83791D has connectable w5 5fxx to store voice data. to expand the storage capacity, users can select many w55fxx to connect with each other. the maximum capacity could be up to 16mbit. following is the connection chart of w55fx with W83791D.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 13 figure 4. speech function diagram 6.3.4 speaker output speech output pin is a 8 bit current d/a converter, with which loading is needed. the resistor could range from 510~1k ohm and bipolar could b e a low power npn bipolar with ] of 120 - 160 . usually, an 8050d transistor is appropriate. the spec of speaker is 8 w . besides, spk can also connect to ac97 codec chip line_out. c is decouple capacitor and is usually 200p - 0.01uf spk 8 ohm speaker 8050d, npn transistor r c figure. 5 data addr clk ctrl mode eop speech synthesizer (W83791D) 9 - bit dac eeprom data addr clk ctrl mode eop eeprom data addr clk ctrl mod e eop slotocc# evttrap 1: 5 internal programmable trigger hardware monitor status trigger spk/led
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 14 6.4 a ddress resolution protocol (arp) introduction as the w8791d is a slave device existing on the system management bus, it must have a unique address to prevent itself from conflicting with the other devices existing on the same bus. in order to solv e the problem of address conflicts, smbus version 2.0 introduces the concept of dynamically assigned address called address resolution protocol (arp). by such mechanism, each device existing on the smbus will be given an unique slave address if it is a arp - capable device. thus, to meet the new spec, W83791D uniquely provides arp compliant function to acquire an unique slave address. the typical process of arp contains several steps, including prepare to arp, reset device, get udid, assign address, and so on. whenever the slave device accepts the command of arp master, it must reply an acknowledgement to the arp master, thus the arp master is able to carry on the next step. in order to provide a mechanism to isolate device for the purpose of address assignm ent, each device must implement a unique device identifier (udid). the udid is a 128 - bit number comprised of several field, including device capabilities, version revision, vendor id, device id, interface, subsystem vendor id, subsystem device id, and vend or specific id. after the udid of the device is sent to the arp master, the arp master will then assign a random address not in the used address pool to the device generally speaking, there are eleven possible commands to read /write the data of smbus dev ice, and a slave device may use any or all of the eleven protocols to communicate. these protocols are quick command, send byte, receive byte, write byte, write word, read byte, read word, process call, block write, and block write - block read process call. W83791D itself supports the block write - block read process with pec to communicate with arp master. following is a description of the smbus packet protocol diagrams element key.. not all protocol elements will be present in every c ommand, that is, not a ll packets are required to include the packet error code. 1 - bit 7 1 1 8 1 8 1 1 - bit s slave address wr a command a pec a p s start condition sr repeated start condition rd read (bit value of 1) wr write (bit value of 0) a acknowledge (this bit position may be ?0? for an ack or ?1? for a nack) p stop condition pec packet error code master - to - slave slave - to - master
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 15 relative command list: slave address command description c2h 01h prepare to arp c2h 02h reset device (general) c2h 03h get udid (general) c2h 04h assign address c2h slave_addr | 1 direct get udid c2h slave_ addr | 0 direct reset c2h 05h - 1fh reserved. following is an example of the block write - block read process call. the block write - block read process call is a two - part message. it begins with a salve address and a write condition. after the command code the host issues a write count m that describes how many more bytes will be written in the first part of the message. the second part of the message is a block o f read data beginning with a repeated start condition followed by thee salve address and a read bit. the next read byte count n indicates how many more data will be read in the second part of the message. note that the combined data payload must not exceed 32bytes. besides, W83791D also provides packet error code (pec) to insure the accuracy during data transmission. 1 7 1 1 8 1 8 1 8 1 s slave address wr a command code a byte count=m a data byte 1 a ? 8 1 ? 8 1 data byte 2 a ? data byte m a ? 1 7 1 1 8 1 8 1 1 sr slave address rd a byte count=n a data byte 1 a ? 8 1 ? 8 1 8 1 1 data byte 2 a ? data byte n a pec a p
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 16 6.5 asf(alert standard format) introduction in order to implement network management in os - absent, W83791D provides asf response registers to meet asf sensor spec. as a result, the network server is able to monitor several environmental status of the client in os - absent by pet frame values returned from W83791D, including temperature, voltage, fan speed, and case open. in below is the asf diagram: figure 6. asf block diagram 6.5.1 platform event trap (pet) pet is the asf transmit protocol used to provide common fields for trap regardless of trap source. the variable bindings fields in a pet frame contain the system and sensor information for an event, such as event sensor type, event type, event offset, event source type, sensor device, sensor number, entity id, entity instance, event status index, event sta tus, and event severity. each field has its definition and is described in the following table. p p c c i i b b u u s s m m o o t t h h e e r r b b o o a a r r d d s s m m b b u u s s m m a a n n a a g g e e m m e e n n t t s s e e r r v v e e r r 791 d c c h h i i p p s s e e t t polling ( pet subset) slave lan on card alert message lan on board
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 17 pet variable binding field description event sensor type the event sensor type field indicates what types of events the sensor is monitoring. e.g. temperat ure, voltage, fan, etc. event type the event type indicates what type of transition/state change triggered the trap. event offset the event offset indicates which particular event occurred for a given even type. event source type the event source type d escribes the originator of the event. it is asf1.0(68h) for all pet frames defined by this specification. sensor device the sensor device is the smbus address of the sensor that caused the event for the pet frame. sensor number the sensor number is used to identify a given instance of a sensor relative to the sensor device. entity id the entity id indicates the platform entity the event is associated with. e.g. processor, system board, etc. entity instance the entity instance indicates which instance o f the entity the event is for. e.g. processor 1 or processor 2. event status index the event status index identifies a unique event monitored by the asf - sensor. it is zero - based, sequential, continuous, and ranging form 0 - 37h. event status the event st atus indicates the event state of the asf - sensor device associated with the message?s event status index. event severity the event severity gives the management station an indication of the severity of the event in the pet frame. typical values are monito r (0x01), non critical (0x08), or critical condition (0x10).
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 18 following is the illustration of asf smbus command for get event data. 1 7 1 1 8 1 8 1 s slave address wr a command a wr byte count a ? asf - sensor address 0 0 sensor device 0000 0001 0 0 000 0100 0 8 1 8 1 8 1 8 1 wr data 1 a wr data 2 a wr data 3 a wr data 4 a ? sub command get event data 0001 0001 0 version number 0001 0000 0 event status index 00ii iiii 0 reserved 0000 0000 0 1 7 1 1 8 1 sr slave address r a rd byte count a ? asf - sensor address 1 0 0000 1010 to 0000 1111 0 1 8 1 8 1 8 1 a rd data 1 a rd data 2 a rd data 3 a ? 0 status 0 event sensor type 0 event type 0 8 1 8 1 8 1 8 1 rd data 4 a rd data 5 a rd data 6 a rd data 7 a ? event offset 0 event source type 0 event severity 0 sensor device 0 8 1 8 1 8 1 rd data 8 a rd data 9 a rd data 10 a ? sensor number 0 entity 0 entity instance 0 8 1 1 ? pec a p from zero to five bytes of event data [data dependent] 1
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 19 6.6 analog inputs the maximum input voltage of the analog pin is 4.096v because the 8 - bit adc has a 16mv lsb. actually, the application of the pc monitoring would most often be connected to power supply. the cpu v - core voltage,+3.3v and battery voltage can directly connect to these analog i nputs. the ? 5v, ? 12v and +12v inputs should be reduced a factor with external resistors to meet the input range. as figure 7 shows. pin 36 +1.8vcore +1.5vinr0 pin 35 +3.3vin 12vin pin 34 pin 32 pin 33 vinr1 n12vin vbat pin 31 pin 30 r6 r1 v1 n5vin positive inpu t negative input 8 - bit adc with 16mv lsb typical thermister connection 10k, 1% r thm vref pin 37 vtin3 vtin2 vtin1 pin 38 pin 39 pin 40 pin 29 pin 28 positive inputs r5 r7 r8 10k, 25 c **the connections of vtin1 and vtin2 are sa me as vtin3 r2 5vsb r v3 v4 figure 7. 6.6.1 monitor over 4.096v voltage: the input voltage +12vin can be expressed as the following equa tion. 2 1 2 1 12 r r r v vin + = the value of r1 and r2 can be selected to 28k ohms and 10k ohms, respectively, when the input voltage v1 is 12v. the node voltage of +12vin should be subject to under 4.096v for the maximum input range of the 8 - bit adc. the pin 13 a nd pin 29 are discretely connected to the power supply +5v and 5vsb . there are two functions in these pins with 5v. the first function is to supply internal analog power in the W83791D and the second one is that these voltages are all connected to interna l serial resistors to monitor the +5v and 5vsb voltage.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 20 6.6.2 monitor negative voltage: the negative voltage should be connected to two series resistors and a positive voltage vref (equal to 3.6v). in the figure 11, the voltage v 3 and v4 are two negative vol tages and are - 12v and - 5v respectively. the voltage v3 is connected to two serial resistors as well as another positive terminal vref. therefore, the voltage node n12vin would be a positive voltage if the scale of the two serial resistors are carefully se lected. it is recommended from winbond that the scale of the two serial resistors are r5=232k ohms and r6=56k ohm. the input voltage of node - 12vin can be calculated by the following equation. n vin vref v k k k v 12 232 232 56 5 5 = + + + ( ) ( ) w w w where vref is equal to 3.6v. if the v 5 i s equal to - 12v then the voltage is equal to 0.567v and the converted hexdecimal data is set to 35h by the 8 - bit adc with 16mv - lsb.this monitored value should be converted to the real negative voltage and the express equation is shown as follows. v n vin vref 5 12 1 = - - b b where b is 232k /(232k+56k). if the n2vin is 0.567 then the v5 is approximately equal to - 12v. the other negative voltage input v6 (approximate - 5v) can also be evaluated by the similar method and the serial resistors can be r 7=120k ohms and r8=56k ohms by the winbond recommended. the expression equation of v6 with - 5v voltage is shown as follows. v n vin vref 6 5 1 = - - g g where the b is set to 120k/(120k+56k). if the monitored adc value in the n5vin channel is 0 .8635, vref=3.6v and the parameter b is 0.6818, then the negative voltage of v6 can be evaluated - 5v.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 21 6.7 fan speed count and fan speed control 6.7.1 fan speed count W83791D support 5 sets of fan counting. fan inputs are provided for signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and the maximum input voltage should not be over +5.5v. if the input signals from the tachometer outputs are over the vcc, the external trimming circuit shou ld be added to reduce the voltage to meet the input specification. the normal circuit and trimming circuits are shown as figure 8. determine the fan counter according to: divisor rpm count = 6 10 35 . 1 in other words, if the fan speed counter has been read from regis ter cr[28] or cr[29] or cr[2a] or cr[ba] or cr[bb] , then the fan speed can be evaluated by the following equation. divisor count rpm = 6 10 35 . 1 the default divisor is 2 and defined at cr47.bit7~4, cr4b.bit7~6, and bank0 cr5d.bit5~7 which are three bits for divisor. this provides very low speed fan counter such as power supply fan. the followed table is an example for the relation of divisor, rpm, and count. divisor nominal rpm time per revolution counts 70% rpm time for 70% 1 8800 6.82 ms 153 6160 9.74 ms 2 (d efault) 4400 13.64 ms 153 3080 19.48 ms 4 2200 27.27 ms 153 1540 38.96 ms 8 1100 54.54 ms 153 770 77.92 ms 16 550 109.08 ms 153 385 155.84 ms 32 275 218.16 ms 153 192 311.68 ms 64 137 436.32 ms 153 96 623.36 ms 128 68 872.64 ms 153 48 1246.72 ms tab le 2.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 22 fan connector fan out +12v gnd pull - up resister 4.7k ohms +5v +12v fan input pin 18/19/20 W83791D fan connector fan out +12v gnd pull - up resister 4.7k ohms +12v fan input pin 18/19/20 W83791D 14k~39k 10k figure 8 - 2. fan with tach pull - up to +12v, or totem - pole output and register attenuator figure 8 - 1. fan with tach pull - up to +5v fan conne ctor fan out +12v gnd pull - up resister > 1k +12v fan input pin 18/19/20 W83791D fan connector fan out +12v gnd pull - up resister < 1k or totem - pole output +12v fan input pin 18/19/20 W83791D > 1k figure 8 - 4. fan with tach pull - up to +1 2v, or totem - pole putput and zener clamp figure 8 - 3. fan with tach pull - up to +12v and zener clamp 3.9v zener 3.9v zener 6.7.2 fan speed control the W83791D provides five sets of pwm for fan speed control. the duty cycle of pwm can be programmed by a 8 - bit registers defined in the bank0 cr[81], cr[83], cr[94], cr[9e] and cr[9f] . the default dut y cycle is set to 100%, that is, the default 8 - bit register is set to 0xffh. the expression of duty cycle can be represented as follows. duty cycle programmed 8 - bit regist er value 255 - = (%) 100%
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 23 +12v fan r1 r2 nmos pnp transistor c + - pwm clock input d s g figure 9. 6.7.3 smart fan control W83791D supports three smart fan function and mapping to te mp1 (fan1, pwmout1), temp2 (fan2, pwmout2) , temp3( fan3, pwmout3) .smart fan control provides two mechanisms. one is thermal cruise mode and the other is fan speed cruise mode. 6.7.3.1 thermal cruise mode at this mode, W83791D provides the smart fan system to a utomatically control fan speed to keep the temperatures of cpu and the system within specific range. at first a wanted temperature and interval must be set (ex. 55 c 3 c) by bios and the fan speed will be lowered as long as the current temperature rem ains below the setting value. once the temperature exceeds the high limit ( 58 c), the fan will be turned on with a specific speed set by bios (ex: 80% duty cycle) and automatically controlled its pwm duty cycle with the temperature varying. three conditio ns may occur : (1) if the temperature still exceeds the high limit (ex: 58 c), pwm duty cycle will increase slowly. if the fan has been operating in its full speed but the temperature still exceeds the high limit (ex: 58 c), a warning message will be issu ed to protect the system. (2) if the temperature goes below the high limit (ex: 58 c), but still above the low limit (ex: 52 c), the fan speed will be fixed at the current speed because the temperature is in the target range (ex: 52 c ~ 58 c). (3) if the temperature goes below the low limit (ex: 52 c), pwm duty cycle will decrease slowly to 0 or a preset stop value until the temperature exceeds the low limit. figure 10 - 1, 10 - 2 gives an illustration of thermal cruise mode. 55`c 58`c 52`c pwm duty cycle 100 0 50 fan start = 20% a b c d figure 10 - 1.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 24 55`c 58`c 52`c pwm duty cycle 100 0 50 fan start = 20% fan stop = 10% fan start = 20% a b c d figure 10 - 2. 6.7.3.2 fan speed cruise mode at this mode, W83791D provides the smart fan system to automatically control the fan speed within a specific range. in the beginning, a wanted fan speed count and interval must be set (ex. 160 10 ) by bios. as long as the fan speed count remains in the specific range, pwm duty cycle will keep the current value. if current fan speed count is higher than the high limit (ex. 160+10), pwm duty cycle will be increased to make the count under the high limit. on the other hand, if current fan speed count is less than the low limit(ex. 160 - 10), pwm duty cycle will be decreased to make the count higher than the low limit. see figure 10 - 3 example. 160 170 150 pwm duty cycle 100 0 50 a c count figure 10 - 3. of course, smart fan control sys tem can be disabled and the fan speed control algorithm can be programmed by bios or application software.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 25 6.8 temperature measurement machine the temperature data format is 8 - bit two - complement for sensor 1 and 9 - bit two - complement for sensor 2/3. the 8 - bit temperature data can be obtained by reading the cr[27h]. the 9 - bit temperature data can be obtained by reading the 8 msbs from the bank0 cr[c0/ c8h] and the lsb from the bank0 cr[c1/c9h] bit 7. the format of the temperature data is show in table 3. tem perature 8 - bit digital output 9 - bit digital output 8 - bit binary 8 - bit hex 9 - bit binary 9 - bit hex +125 c 0111,1101 7dh 0,1111,1010 0fah +25 c 0001,1001 19h 0,0011,0010 032h +1 c 0000,0001 01h 0,0000,0010 002h +0.5 c - - 0,0000,0001 001h +0 c 0000,000 0 00h 0,0000,0000 000h - 0.5 c - - 1,1111,1111 1ffh - 1 c 1111,1111 ffh 1,1111,1110 1ffh - 25 c 1110,0111 e7h 1,1100,1110 1ceh - 55 c 1100,1001 c9h 1,1001,0010 192h table 3. 6.8.1 monitor temperature from thermistor: the W83791D can connect three thermistors t o measure three different environmental temperatures. the specification of thermistor should be considered to (1) b value is 3435k, (2) resistor value is 10k ohms at 25 c. in the figure 11, the themistor is connected by a serial resistor with 10k ohms(1% e rror), then connect to vref (pin 37). 6.8.2 monitor temperature from pentium ii tm thermal diode or bipolar transistor 2n3904 the W83791D can alternate the thermistor to pentium ii/iii tm thermal diode interface or transistor 2n3904 and the circuit connection is shown as figure 11. the pin of pentium ii/iii tm d - is connected to power supply ground (gnd) and the pin d+ is connected to pin piitdx in the W83791D. the resistor r=30k ohms should be connected to vref to supply the diode bias current and the bypass capa citor c=3300pf should be added to filter the high frequency noise. the transistor 2n3904 should be connected to a form with a diode, that is, the base (b) and collector (c) in the 2n3904 should be tied together to act as a thermal diode.
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 26 2n3904 c e b r=30k, 1% c=3300pf bipolar transistor temperature sensor pentium ii/iii cpu d+ d - therminal diode c=3300pf r=30k, 1% vref piitdx piitdx or W83791D figure 11. 6.8.3 smi# interrupt for W83791D voltage smi# interrupt for voltage is two - times interrupt mode. voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading a ll the interrupt status register. (figure 12 - 1.) 6.8.4 smi# interrupt for W83791D fan smi# interrupt for fan is two - times interrupt mode. fan count exceeding the limit, or exceeding and then going below the limit (set at value ram index 3bh and 3ch) , will caus es an interrupt if the previous interrupt has been reset by reading all the interrupt status register. (figure 12 - 2.)
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 27 * * * figure 12-1. voltage smi# mode *interrupt reset when interrupt status registers are read figure 12-2. fan smi# mode smi# * high limit low limit * smi# * fan count limit 6.8.5 smi# interrupt for W83791D temperature sensor 1/2/3 (1) comparator interrupt mode temp erature exceeding t o causes an interrupt and this interrupt will be reset by reading all the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will occur a gain when the next conversion has completed. if an interrupt event has occurred by exceeding t o but has not been reset, the interrupts will not occur again. the interrupts will continue to occur in this manner until the temperature goes below t hyst . (fig ure 12 - 3.) (2) two - times interrupt mode temperature exceeding t o causes an interrupt and then temperature going below t hyst will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt status register. once an interr upt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will not occur. (figure 12 - 4.) (3) one - time interrupt mode temperature exceeding t o causes an interrupt and then temperature going below t hyst will not cause an interrupt. once an interrupt event has occurred by exceeding t o , then going below t hyst, an interrupt will not occur again until the temperature exceeding t o . (figure 12 - 5.)
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 28 t oi t hyst * * * figure 12 - 3. comparator interrupt mode *interrupt reset when interrupt status registers are read t oi t hyst figure 12 - 4. two - t imes interrupt mode smi# smi# * * * * * *interrupt reset when interrupt status registers are read t oi t hyst figure 12 - 5. one - time interrupt mode smi# * * note. the irq interrupt action like smi# , but the irq is level signal. 6.8.6 over - temperature (ovt#) for W83791D temperature sensor 1/2/3 (1) comparator mode: temperature exceeding t o causes the ovt# output activated until the temperature is l ess than t hyst . (figure 13) (2) interrupt mode: temperature exceeding t o causes the ovt# output activated indefinitely until reset by reading temperature sensor 1 or sensor 2 or sensor 3 registers. temperature exceeding t o , then ovt# reset, and then temp erature going below t hyst will also cause the ovt# activated indefinitely until reset by reading temperature sensor 1 or sensor 2 or sensor 3 registers. once the ovt# is activated by exceeding t o , then reset, if the temperature remains above t hyst , the ovt # will not be activated again.( figure 13) (3) acpi mode
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 29 at this mode, temperature exceeding one level of temperature separation, starting from 0 degree, causes the ovt# output activated. ovt# will be activated again once temperature exceeds the next l evel. ovt# output will act the same manner when temperature goes down. (figure 13 - 1). the granularity of temperature separation between each ovt# output signal can be programmed at bank0 cr[4ch] bit 4 - 5. t hyst * * figure 13 over - temperature response diagram *interrupt reset when temperature 1/2/3 is read ovt# ovt# * (comparator mode; default) (interrupt mode) to 0 10 20 30 40 50 100 90 80 70 60 ovt# ('c) current temperature figure 13 - 1. acpi mode
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 30 8 electrical character istics 9.1 absolute maximum ratings parameter rating unit power supply voltage - 0.5 to 7.0 v input voltage - 0.5 to v dd +0.5 v operating temperature 0 to +70 c storage temperature - 55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 9.2 dc char acteristics (ta = 0 c to 70 c, v dd = 5v 10%, v ss = 0v) parameter sym . min . typ. max. unit conditions i/o 12t - ttl level bi - directional pin with source - sink capability of 12 ma input low voltage v il 0.8 v input high voltage v ih 2.0 v output l ow voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = - 12 ma input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0v i/o 12ts - ttl level bi - directional pin with source - sink capability of 12 ma and schmitt - trigger level input input low threshold voltage v t - 0.5 0.8 1.1 v v dd = 5 v input high threshold voltage v t+ 1.6 2.0 2.4 v v dd = 5 v hysteresis v th 0.5 1.2 v v dd = 5 v output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = - 12 ma input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0v
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 3 1 7.2 dc characteristics, continued parameter sym . min. typ. max. unit conditions out 12t - ttl level output pin with source - sink capability of 12 ma outpu t low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = - 12 ma od 8 - open - drain output pin with sink capability of 8 ma output low voltage v ol 0.4 v i ol = 8 ma od 12 - open - drain output pin with sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma od 48 - open - drain output pin with sink capability of 48 ma output low voltage v ol 0.4 v i ol = 48 ma in t - ttl level input pin input low voltage v il 0.8 v input high voltage v ih 2.0 v input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0 v in ts - ttl level schmitt - triggered input pin input low threshold voltage v t - 0.5 0.8 1.1 v v dd = 5 v input high threshold voltage v t+ 1.6 2.0 2.4 v v dd = 5 v hysteresis v th 0.5 1.2 v v dd = 5 v input high leakage i lih +10 m a v in = v dd input low leakage i lil - 10 m a v in = 0 v
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 32 9.3 ac characteristics 9.3.1 serial bus timing diagram valid data scl sda in sda out t hd;sda t scl t su;dat t su;sto serial bus timing diagram t r t r t hd;dat serial bus timing parameter symbol min. max. unit scl clock period t - scl 10 us start condition hold time t hd;sda 4.7 us stop condition setup - up time t su;sto 4.7 us data to scl setup time t su;dat 120 ns data to scl hold time t hd;dat 5 ns scl and sda rise time t r 1.0 us scl and sda fall time t f 300 ns
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 33 10 how to read the top marking the top marking of W83791D W83791D 025aa left: winbond logo 1st line: type number W83791D, d means lqfp (thickness = 1.4 mm). 2nd line: tracking code 025 a a 025 : packages made in 2000, week 25 a : assembly house id; a mean s ase, o means ose a : ic revision; a means version a, b means version b
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 34 11 package specificatio n (48 - pin qfp) 2 1 a h d d e b e h e y a a seating plane l l 1 see detail f detail f c 37 48 1 12 13 24 25 36 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 1.40 0.20 0.50 1.00 7.00 9.00 9.00 7.00 --- --- --- 1.60 0.15 1.45 1.35 0.05 0.17 0.27 --- 0.09 0.20 0.45 0.60 0.75 0.08 0 3.5 7 --- --- headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 please note that all data and specifications are subject to change without noti ce. all the trade marks of products and companies mentioned in this data sheet belong to their respective owner
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 35 0.2 w83782d-W83791D application circuit custom 1 5 tuesday, may 22, 2001 title size document number rev date: sheet of vcc +12v +5vsb 3vcc vcc -12v vcc +5v 5vsb +5v 3vsb -5v 5vsb 5vsb 3vcc vcore vinr0 3vin gnda gnda adrmselin sda scl sda vid2 out3/vid90 adrmselin rext/clkin eop/iow# beep gndd vdd adrmselin gnda gnda vcore vid4 -12vin vid3 -12vin +12vin vinr0 vinr1 gnda -5vin -5vin vid0 ovt# vbat +12vin gnda smi#/led vref +5vsb vref gnda beep 3vin +5vsb vinr1 scl gndd pwmout2/d0 data/d5 spk/d2 pwmout1/d1 ctrl/d4 vid1 addr/d7 mode/d3 ckout/d6 smi# smi# ovt# led led smi# smi#/led r2 r 10k r3 r 10k r4 r 28k 1% r5 r 10k 1% ls1 buzzer r33 r 330 r32 r 330 r30 r 4.7k r31 r 4.7k r1 r 10k l3 inductor fb r10 r 56k 1% r12 r 56k 1% r11 r 232k 1% r40 r 510 r38 r 100 r39 r 10k c5 cap 10u c6 cap 0.1u r16 r 0/791d r14 r 0/782d r26 r 0/791d r27 r 0/782d q1 npn 3904 r35 r 0 r37 r 0 r42 r 0 r36 r 0 r43 r 0 r41 r 0 r6 r 34k 1%/791d 0 /782d r8 r 5.1k 1%/782d 0 /791d r7 r 50k 1%/791d r9 r 7.5k 1%/782d c2 cap 0.1u/791d c4 cap 0.1u/782d c3 cap 10u/782d r19 r 0/782d r17 r 0/791d r15 r 10k/791d c1 cap 10u/791d r13 r 120k 1% r34 r 220k/ 791d l1 inductor fb/791d l2 inductor fb/782d winbond electronics corp. r18 0/791d r22 0/791d r23 0/791d r24 0/791d r29 0/791d r28 0/791d r25 0/791d u1 W83791D 37 38 39 40 41 42 43 44 45 46 47 48 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 2 vref vtin3/piitd3 vtin2/piitd2 vtin1/piitd1 vid0 ovt# irq/gpio10 smi#/ledout evntrap1/gpio5 evntrap2/gpio6/fanin4 evntrap3/gpio7/fanin5 evntrap4/gpio8/pwmout4 rext addr/gpio0 clkout/gpio1 data/gpio2 ctrl/gpio3 mode/gpio4 speaker/led/speech_sel pwmout1/a0 pwmout2/a1 vid1 vdd gndd slotocc# caseopen vid4 fanin3 fanin2 fanin1 scl sda pwmout3/vid_v90 vid2 vid3 beep gnda -5vin +5vsb vbat -12vin +12vin vinr1 +3.3vin vinr0 vcore evntrap5/gpio9/pwmout5 eop/gpio11 r? 270 q? mosfet n 2n7000 d? led r129 0 r130 0/791d,b r20 r 4.7k r21 r 4.7k r131 0/791d,b u7a 7404 /791d, b 1 2 r? 1k r? 0 r? 0/791d gtlvolt 3vcc smclk smdat cs# t1 t2 t3 cpuvcoa gnda sa2 sa1 sa0 ia2 ia1 ia0 fan1in caseopen fan2in irq/gpio10 fan3in mr# slotocc# evnt2/a1 evnt3/a0 evnt1/a2 evnt2/a1 evnt3/a0 evnt1/a2 evnt2/a1 evnt3/a0 evnt1/a2 pwmout5 evnt5/ior# pwmout4 evnt4 fan4in fan5in extsmi# thrm# beep circuits voltage sensing bits of isa address bus set a2-a0 as 3 lowest order set a2-a0 as bit2, bit1, bit0 of 7 bit i2c address setting (for 782d) select one of the two setting. (from pii/piii cpu) 0: means cpu is present 1: means cpu is absent /782d : only for w83782d /791d : only for W83791D (fan) (fan) (fan) (fan) (evnt2) (evnt3) (evnt4) (evnt5) { to chipset !!only for 791d ver b. smi#/ledout function circuit
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 36 0.2 w83782d-W83791D application circuit custom 2 5 tuesday, may 22, 2001 title size document number rev date: sheet of +12v +12v +12v vsb vsb +12v +12v pwmout2/d0 pwmout1/d1 out3/vid90 out3/vid90 out3/vid90 t rt2 thermistor 10k 1% c9 capacitor 3300p jp2 header 3 1 2 3 jp1 header 3 1 2 3 r47 r 10k 1% r53 r 10k 1% d1 diode 1n4148 r48 r 4.7k r50 r 27k r52 r 10k d2 diode 1n4148 r56 r 4.7k r57 r 27k r59 r 10k jp3 header 3 1 2 3 d3 diode 1n4148 r65 r 4.7k r66 r 27k r68 r 10k r58 r 0 r55 r 1k r46 r 1k r44 r 4.7k q4 pnp 3906 q2 pnp 3906 r60 r 30k 1% + c7 47u q3 mosfet n 2n7002 q5 mosfet n 2n7002 + c8 47u r45 r 47k/791d r51 r 0 r61 r 47k/791d q7 mosfet n 2n7002 q6 pnp 3906 r54 r 4.7k r62 r 4.7k r67 r 0 r64 r 1k + c10 47u r49 r 10k 1% t rt4 thermistor 10k 1% r63 r 10k 1% r72 r 47k /791d r74 r 47k /791d t rt3 thermistor 10k 1% t rt1 thermistor 10k 1% jp4 header 3 1 2 3 d4 diode 1n4148 r71 r 4.7k r73 r 27k r76 r 10k q9 mosfet n 2n7002 q8 pnp 3906 r69 r 4.7k r75 r 0 r70 r 1k + c11 47u jp5 header 3 1 2 3 d5 diode 1n4148 r79 r 4.7k r80 r 27k r82 r 10k q11 mosfet n 2n7002 q10 pnp 3906 r77 r 4.7k r81 r 0 r78 r 1k + c12 47u winbond electronics corp. vref t1 t2 t3 gnda d+ d- t2 gnda vref fan1in fan2in fan3in vref gnda t2 fan5in fan4in pwmout4 pwmout5 (for system) (for cpu1) (from pii/piii cpu) temperature sensing (for cpu2) pwm circuit for fan1-3 speed control measuring cpu temperature by either thermistor or diode. r45,r61 in order to trap address be a0=1,a1=0 (for cpu2) select one of the two vid table setting. 0:old vid table(vrm 8.3) 1:new vid table(vrm 9.0) select vid table pwm circuit for fan4-5 speed control when select these pin to pwmout/fan function
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 37 0.2 w83782d-W83791D application circuit b 3 5 tuesday, may 22, 2001 title size document number rev date: sheet of 3vcc vbat addr/d7 data/d5 ctrl/d4 pwmout1/d1 pwmout2/d0 eop/iow# rext/cklin ckout/d6 spk/d2 mode/d3 vid4 vid2 vid0 vid1 vid3 r88 r 0 r94 r 0 r96 r 0 r102 r 0 r103 r 0 r91 r 0 r90 r 0 r89 r 0 r92 r 0 r98 r 0 r100 r 0 r83 r 10k r84 r 10k r85 r 10k r86 r 10k r87 r 10k r93 1k r99 1k r101 1k r95 1k r97 1k u2b 74hc14 /791d 3 4 c13 cap 1000p /791d u2a 74hc14 /791d 1 2 s1 caseopen sw r104 r 0/782d r110 r 0/791d r108 r 0/791d r109 r 0/782d r107 r 10k/791d r105 r 0/791d r111 r 2.2m/791d r106 r 2m/782d winbond electronics corp. ior# iow# clkin sd[0..7] piivid4 piivid3 piivid2 piivid1 piivid0 vid0 vid1 vid2 vid3 vid4 caseopen caseopen evnt5/ior# } to power regulator cpu voltage id input/output circuits for 782d (from cpu) case open circuits these two inverters consume vbat
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 38 0.2 w83782d-W83791D application circuit custom 4 5 tuesday, may 22, 2001 title size document number rev date: sheet of vcc vcc vcc vcc spk/d2 spk/d2 spk/d2 data/d5 eop/iow# ctrl/d4 addr/d7 mode/d3 ckout/d6 ctrl/d4 mode/d3 ckout/d6 data/d5 eop/iow# addr/d7 ls2 8 ohm speaker c17 0.1uf q12 npn 8050d j1 line_out r114 470k r116 470k c16 100pf c19 100pf c15 1uf/16v c18 1uf/16v r112 510 c14 1uf/16v r115 510 r113 270 q13 mosfet n 2n7000 d6 led u5 w55f10 1 2 3 4 5 6 7 8 eop ctrl vss addr data clk vdd mode u6 w55f10 1 2 3 4 5 6 7 8 eop ctrl vss addr data clk vdd mode u3 w55f10 1 2 3 4 5 6 7 8 eop ctrl vss addr data clk vdd mode r125 0/791d r124 0/791d r118 0/791d r120 0/791d r119 0/791d r122 0/791d u4 w55f10 1 2 3 4 5 6 7 8 eop ctrl vss addr data clk vdd mode r128 0/791d r117 0/791d r123 0/791d r121 0/791d r126 0/791d r127 0/791d winbond electronics corp. line_out_l line_out_r connect to serial flash eeprom (w55fxx) /791d connect 1 flash connect 2 or more flash from ac' 97 codec (w83971d) select speech / led function by one of three cricuits. / 791d 1. 2. 3. (led function) (speech function) (speech function)
W83791D preliminary p ublication release date: aug , 2001 revision 0. 4 1 39 0.2 w83782d-W83791D application circuit a 5 5 tuesday, may 22, 2001 title size document number rev date: sheet of winbond electronics corp. rev 0.1 decription first publication 0.15 add fan/pwmout4-5 circuit 0.16 change r34 connect to 5vsb 0.17 1. change r32/r33 value to 330 ohm 2. modify r34 value as 220k ohm 3. change smi# (pin 44) circuit. this update is for b version. 0.2 update pin44 (smi#/ledout) circuit. this update is for c version.

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